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TM
CDP1852, CDP1852C
Byte-Wide Input/Output Port
Description
The CDP1852 and CDP1852C are parallel, 8-bit, mode-programmable input/output ports. They are compatible and will interface directly with CDP1800-series microprocessors. They are also useful as 8-bit address latches when used with the CDP1800 multiplexed address bus and as I/O ports in generalpurpose applications. The mode control is used to program the device as an input port (mode = 0) or as an output port (mode = 1). The SR/SR output can be used as a signal to indicate when data is ready to be transferred. In the input mode, a peripheral device can strobe data into the CDP1852, and microprocessor can read that data by device selection. In the output mode, a microprocessor strobes data into the CDP1852, and handshaking is established with a peripheral device when the CDP1852 is deselected. In the input mode, data at the data-in terminals (DI0-DI7) is strobed into the port's 8-bit register by a high (1) level on the clock line. The negative high-to-low transition of the clock latches the data in the register and sets the service request output low (SR/SR = 0). When CS1/CS1 and CS2 are high (CS1/CS1 and CS2 = 1), the three-state output drivers are enabled and data in the 8-bit register appear at the data-out terminals (D00-D07). When either CS1/CS1 or CS2 goes low (CS1/CS1 or CS2 = 0), the data-out terminals are three-stated and the service request output returns high (SR/SR =1). In the output mode, the output drivers are enabled at all times. Data at the data-in terminals (DI0-DI7) is strobed into the 8-bit register when CS1/CS1 is low (CS1/CS1 = 0) and CS2 and the clock are high (1), and are present at the data-out terminals (D00-D07). The negative high-to-low transition of the clock latches the data in the register. The SR/SR output goes high (SR/SR = 1) when the device is deselected (CS1/CS1 = 1 or CS2 = 0) and returns low (SR/SR = 0) on the following trailing edge of the clock.
March 1997
Features
* Static Silicon-Gate CMOS Circuitry * Parallel 8-Bit Data Register and Buffer * Handshaking Via Service Request Flip-Flop * Low Quiescent and Operating Power * Interfaces Directly with CDP1800-Series Microprocessors * Single Voltage Supply * Full Military Temperature Range (-55oC to +125oC)
Ordering Information
PACKAGE TEMP. RANGE PDIP SBDIP 5V 10V PKG. NO. E24.6
-40oC to +85oC CDP1852CE CDP1852E
-40oC to +85oC CDP1852CD CDP1852D D24.6
Pinout
24 LEAD DIP TOP VIEW
CSI/CSI 1 MODE 2 DI0 3 DO0 4 DI1 5 DO1 6 DI2 7 DO2 8 DI3 9 DO3 10 CLOCK 11 VSS 12 24 VDD 23 SR/SR 22 DI7 21 DO7 20 DI6 19 DO6 18 DI5 17 DO5 16 DI4 15 DO4 14 CLEAR 13 CS2
Typical CDP1802 Microprocessor System
CLEAR WAIT
ADDR BUS TPA
ADDR BUS TPA CPU CDP1802 MRD MWR
N0 - N2 MRD TPB Q SC0 SC1 INTERRUPT I/O CDP1852 DATA CONTROL
ROM MRD CEO
RAM
DMA - IN DMA - OUT EF1 - EF4
BIDIRECTIONAL DATA BUS
FIGURE 1.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1
File Number
1166.2
CDP1852, CDP1852C
Absolute Maximum Ratings
DC Supply-voltage Range, (VDD) (Voltage Referenced to VSS Terminal) CDP1852 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +11V CDP1852C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . 10mA Device Dissipation Per Output Transistor. . . . . . . . . . . . . . . 100mW For TA = Full Package-Temperature Range (All Package Type)
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 65 N/A SBDIP Package. . . . . . . . . . . . . . . . . . 65 20 Operating-Temperature Range (TA) Package Type D, H . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering): . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 inch (1.59 0.79mm) from Case for 10s max
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
At TA = Full Package Temperature Range. For Maximum Reliability, Operating Conditions Should be Selected so that Operation is Always within the Following Ranges: LIMITS CDP1852 CDP1852C MAX 10.5 VDD MIN 4 VSS MAX 6.5 VDD UNITS V V
PARAMETER DC Operating Voltage Range Input Voltage Range
MIN 4 VSS
Functional Diagram
CSI/CSI (NOTE 1) CS2 MODE CLOCK CLEAR 1 DEVICE SELECT DECODE CONTROL LOGIC 23 SR/SR (NOTE 1)
13 2 11 14
24 12
VDD VSS
MODE 0 P1 P23 CSI SR
MODE 1 CSI SR
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
3 5 7 9 16 18 20 22
RESET
CLOCK
ENABLE THREESTATE OUTPUT DRIVERS
8-BIT DATA REGISTER
4 6 8 10 15 17 19 21
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
NOTE: 1. Polarity depends on mode. FIGURE 2. FUNCTIONAL BLOCK DIAGRAM FOR CDP1852
A CLEAR control is provided for resetting the port's register (DO0-DO7 = 0) and service request flip-flop (input mode: SR/ SR = 1 and output mode: SR/SR = 0). The CDP1852 is functionally identical to the CDP1852C. The CDP1852 has a recommended operating voltage range of 4 to 10.5 volts, and the CDP1852C has a recommended operating voltage range of 4 to 6.5 volts. The CDP1852 and CDP1852C are supplied in 24-lead, hermetic, dual-in-line ceramic packages (D suffix), in 24-lead dual-in-line plastic packages (E suffix). The CDP1852C is also available in chip form (H suffix).
2
CDP1852, CDP1852C Logic Diagram
CS2 13 SR/SR CS1/CS1 1 23 S MODE 2 VSS R CL CLEAR 14 SERVICE REQUEST LATCH D Q
CLOCK 11 VDD p DI0 3 p TG n p TG n DO0 4 n
VSS
DO1 DI1 5 6
DO7 DI7 22 21
FIGURE 3. CDP1852 LOGIC DIAGRAM
Static Electrical Specifications
At TA = -40oC to +85oC, Unless Otherwise Specified CONDITIONS CDP1852 VO (V) VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 VDD (V) 5 10 5 10 5 10 5 10 (NOTE1) TYP 3.2 6 -2.3 -6 0 0 LIMITS CDP1852C (NOTE1) TYP 3.2 -2.3 0 -
PARAMETER Quiescent Device Current IDD
MIN 1.6 3 -1.15 -3 -
MAX 10 100 0.1 0.1
MIN 1.6 -1.15 -
MAX 50 0.1 -
UNITS A A mA mA mA mA V V
-
Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low-Level (Note 2)
IOL
0.4 0.5
IOH
4.6 9.5
VOL
-
3
CDP1852, CDP1852C
Static Electrical Specifications
At TA = -40oC to +85oC, Unless Otherwise Specified (Continued) CONDITIONS CDP1852 VO (V) VOH Input Low Voltage VIL 0.5, 4.5 0.5, 9.5 Input High Voltage VlH 0.5, 4.5 0.5, 9.5 Input Leakage Current IlN Three-State Output Leakage Current Operating Current (Note 3) IOUT 0, 5 0, 10 IDD1 Input Capacitance Output Capacitance NOTES: 1. Typical values are for TA = 25oC and nominal VDD. 2. IOL = IOH = 1A 3. Operating current is measured at 2MHz in an CDP1802 system with open outputs and a program of 6N55, 6NAA, 6N55, 6NAA,.... At TA = -40oC to +85oC, VDD = 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF, and 1 TTL Load LIMITS VDD (V) (NOTE 1) TYP CIN COUT VIN (V) 0, 5 0, 10 VDD (V) 5 10 5 (NOTE1) TYP 5 10 LIMITS CDP1852C (NOTE1) TYP 5 -
PARAMETER Output Voltage High Level (Note 2)
MIN 4.9 9.9 -
MAX 1.5
MIN 4.9 -
MAX 1.5
UNITS V V V
-
10
-
-
3
-
-
-
V
-
5
3.5
-
-
3.5
-
-
V
-
10
7
-
1 2 1 2 300 800 7.5 7.5
-
-
1 1 300 7.5 -
V A A A A A A pF pF
0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 -
5 10 5 10 5 10 -
-
130 550 5 5
-
150 5 -
Dynamic Electrical Specifications
PARAMETER MODE 0 - INPUT PORT (See Figure 4) Minimum Select Pulse Width tSW
MIN
MAX
UNITS
5 10
-
180 90 90 45 80 40
360 180 180 90 160 80
ns ns ns ns ns ns
Minimum Write Pulse Width
tWW
5 10
Minimum Clear Pulse Width
tCLR
5 10
4
CDP1852, CDP1852C
Dynamic Electrical Specifications
At TA = -40oC to +85oC, VDD = 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF, and 1 TTL Load (Continued) LIMITS VDD (V) tDS 5 10 Minimum Data Hold Time tDH 5 10 Data Out Hold Time (Note 2) tDOH 5 10 Propagation Delay Times, tPLH, tPHL Select to Data Out (Note 2) tSDO 5 10 Clear to SR tRSR 5 10 Clock to SR tCSR 5 10 Select to SR tSSR 5 10 NOTES: 1. Typical values are for TA = 25oC and nominal VDD. 2. Minimum value is measured from CS2, maximum value is measured from CS1/CS1. 30 15 185 100 170 85 110 55 120 60 370 200 340 170 220 110 240 120 ns ns ns ns ns ns ns ns (NOTE 1) TYP -10 -5 75 35 185 100
PARAMETER Minimum Data Setup Time
MIN 30 15
MAX 0 0 150 75 370 200
UNITS ns ns ns ns ns ns
Input Port Mode 0 - Typical Operation
General Operation When the mode control is tied to VSS, the CDP1852 becomes an input port. In this mode, the peripheral device places data into the CDP1852 with a strobe pulse and the CDP1852 signals the microprocessor that data is ready to be transferred on the strobe's trailing edge via the SR output line. The CDP1802 then issues an input instruction that enables the CDP1852 to place the information from the peripheral device on the data bus to be entered into a memory location and the accumulator of the microprocessor. Detailed Operation (See Figure 5) The STROBE from the peripheral device places DATA into the 8-bit register of the CDP1852 when it goes high and latches the DATA on its trailing edge. The SR output is set low on the strobe's trailing edge. This output is connected to a flag line of the CDP1802 microprocessor and software polling will determine that the flag line has gone low and peripheral data is ready to be transferred. The CDP1802 then issues an input instruction that places an NX line high. With the MRD line also high, the CDP1852 is selected and its output drivers place the DATA from the peripheral device on the DATA BUS. When the CDP1802 selected the CDP1852, it also selected and addressed the memory via one of the 16 internal address registers selected by an internal "X" register. The data from the CDP1852 is therefore entered into the memory [Bus M(R(X))]. The data is also transferred to the D register (accumulator) in the microprocessor (Bus D). When the CDP1802's execute cycle is completed, the CDP1852 is deselected by the NX line returning low and its data output pins are three-stated. The SR output returns high.
5
CDP1852, CDP1852C
CS1 - CS2 (NOTE 1) CLOCK
tSW
tWW tDH
DATA IN tDS DATA BUS HIGH IMPEDANCE tSSR SR tRSR CLEAR tCLR NOTE 1. CS1 * CS2 is the overlap of CS1 = 1 and CS2 = 1. tCSR tSDO tDOH
MODE 0 TRUTH TABLE CLOCK X 0 0 1 CS1-CS2 0 1 1 1 CLEAR X 0 1 X DATA OUT EQUALS High Impedance 0 Data Latch Data In
SERVICE REQUEST TRUTH TABLE CLOCK CS1 or CS2 or CLEAR 0 SR/SR 1
SR/SR
CS1 * CS2: CS1 = 1, CS2 = 1 FIGURE 4. MODE 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
MEMORY
CDP1802 NX ADDRESS LINES MRD EFX VSS
CDP1852 CS2 CLOCK CS1 SR MODE D0 D1
STROBE DATA FROM PERIPHERAL
DATA BUS
STROBE
PERIPHERAL DATA
PERIPHERAL DEVICE PLACES DATA IN CDP1852 AND CDP1852 SIGNALS CDP1802 THAT DATA IS READY
SR/SR
NX CDP1802 SELECTS CDP1852 AND DATA IS TRANSFERRED TO MEMORY AND THE MICROPROCESSOR
MRD
DATA BUS
VALID
THREE - STATE
FIGURE 5. INPUT PORT MODE 0 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION
6
CDP1852, CDP1852C
Dynamic Electrical Specifications
At TA = -40oC to +85oC, VDD = 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF, and 1 TTL Load LIMITS PARAMETER MODE 1- OUTPUT PORT (See Figure 6) Minimum Clock Pulse Width tCLK 5 10 Minimum Write Pulse Width tWW 5 10 Minimum Clear Pulse Width tCLR 5 10 Minimum Data Setup Time tDS 5 10 Minimum Data Hold Time tDH 5 10 Minimum Select-After-Clock Hold Time tSH 5 10 Propagation Delay Times, tPLH, tPHL Clear to Data Out tRDO 5 10 Write to Data Out tWDO 5 10 Data In to Data Out tDDO 5 10 Clear to SR tRSR 5 10 Clock to SR tCSR 5 10 Select to SR tSSR 5 10 NOTE: 1. Typical values are for TA = 25oC and nominal VDD. 130 65 130 65 60 30 -10 -5 75 35 -10 -5 140 70 220 110 100 50 120 60 120 60 120 60 260 130 260 130 120 60 0 0 150 75 0 0 280 140 440 220 200 100 240 120 240 120 240 120 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD (V) MIN (NOTE 1) TYP MAX UNITS
Output Port Mode 1 - Typical Operation
General Operation Connecting the mode control to VDD configures the CDP1852 as an output port. The output drivers are always on in this mode, so any data in the 8-bit register will be present at the data-out lines when the CDP1852 is selected. The N line and MRD connections between the CDP1852 and CDP1802 remain the same as in the input mode configuration, but now the clock input of the CDP1852 is tied to the TPB output of the CDP1802 and the SR output of the CDP1852 will be used to signal the peripheral device that valid data is present on its input lines. The microprocessor issues an output instruction, and data from the memory is strobed into the CDP1852 with the TPB pulse. When the CDP1852 is deselected, the SR output goes high to signal the peripheral device. Detailed Operation (See Figure 7) The CDP1802 issues an output instruction. The NX line goes high and the MRD line goes low. The memory is accessed M(R(X)) BUS and places data on the DATA BUS. This data are strobed into the 8-bit register of the CDP1852 when TPB goes high and latched on the TPB's trailing edge. The valid data thus appears on the CDP1852 output lines. When the CDP1802 output instruction cycle is complete, the NX line goes low and the SR output goes high. SR will remain high until the trailing edge of the next TPB pulse, when it will return low.
7
CDP1852, CDP1852C
tWW (NOTE 2) CS1 CS2 (NOTE 1) tSH CLOCK tDH tDS tCLK
DATA IN tDDO DATA OUT tRDO tWDO SR tRSR tCSR tCLR CLEAR NOTES 1. CS1 * CS2 is the overlap of CS1 = 0 and CS2 = 1. 2. Write is the overlap of CS1 * CS2 and CLOCK. tSSR
MODE 1 TRUTH TABLE CLOCK 0 0 X 1 CS1-CS2 X X 0 1 CLEAR 0 1 1 X 0 Data Latch Data Latch Data In DATA OUT EQUALS CS1 or CS2
SERVICE REQUEST TRUTH TABLE CLOCK or CLEAR SR/SR 1 SR/SR 0
CS1 * CS2 : CS1 = 0, CS2 = 1 FIGURE 6. MODE 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
MEMORY CDP1802 CDP1852 CS2 CS1 CLOCK DATA OUT SR VDD MODE DATA IN DATA OUT TO PERIPHERAL DEVICE SIGNAL THAT INDICATES DATA IS READY
NX
MRD ADDRESS LINES TPB
DATA BUS NX
TPB CDP1852 IS SELECTED AND DATA IS STROBED INTO IT'S REGISTER WITH TPB
MRD
DATA BUS
VALID DATA DATA IS OUTPUTTED FROM THE CDP1852 AND THE PERIPHERAL DEVICE IS SIGNALED
DATA TO PERIPHERAL DEVICE SR/SR
FIGURE 7. OUTPUT PORT MODE 1 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION
8
CDP1852, CDP1852C Application Information
In a CDP1800 series microprocessor-based system where MRD is used to distinguish between INP and OUT instructions, an lNP instruction is assumed to occur at the beginning of every I/O cycle because MRD starts high. Therefore, at the start of an OUT instruction, which uses the same 3-bit N code as that used for selection of an input port, the input device is selected for a short time (see Figure 8).
MRD
This condition forces SR low and sets the internal SR latch (see Figure 3). In a small system with unique N codes for inputs and outputs, this situation does not arise. Using the CDP1853 N-bit decoder or equivalent logic to decode the N lines after TPA prevents dual selection in larger systems (see Figure 9 and Figure 10).
N0
N1
N2
SELECT
6D
65
SR
FIGURE 8. EXECUTION OF A "65" OUTPUT INSTRUCTION SHOWING MOMENTARY SELECTION OF INPUT PORT "D"
N0
2 1 OF 8 DECODER
4 5 6 7 12 11 10 9 EN
N1
3
OUT 0 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7
N2
14
CE TPA TPB CE EN (NOTE 1) OUTPUT
13
CLOCK A 1 (TPA)
Qn
CLOCK B 15 (TPB)
FIGURE 9. CDP1853 TIMING WAVEFORMS NOTE: 1. Output enabled when EN = HIGH. Internal signal shown for reference only (See Figure 1).
FIGURE10. CDP1853 FUNCTIONAL DIAGRAM
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